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Features
* * * * * * * * * *
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation - 1.8 (VCC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 64-byte Page Mode and Byte Write Operation Block Write Protection - Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: >100 Years Green (Pb/Halide-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Waffle Pack, and Bumped Die
SPI Serial EEPROMS
128K (16,384 x 8) 256K (32,768 x 8)
* *
Description
The AT25128B/256B provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead UDFN packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V). The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. Table 0-1.
Pin CS SCK SI SO GND VCC WP HOLD
AT25128B AT25256B
Pin Configurations
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
8-lead UDFN VCC HOLD SCK SI
8 7 6 5 1 CS 2 SO 3 WP 4 GND
8-lead SOIC CS SO WP GND
1 2 3 4 8 7 6 5
8-lead TSSOP VCC HOLD SCK SI CS SO WP GND
1 2 3 4 8 7 6 5
VCC HOLD SCK SI
8-ball VFBGA VCC HOLD SCK SI
8 7 6 5 1 2 3 4
CS SO WP GND
Bottom View
Bottom View
Block Write protection is enabled by programming the status register with top 1/4, top 1/2 or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
8698B-SEEPR-3/10
1.
Absolute Maximum Ratings*
Operating Temperature ........................-55C to +125C Storage Temperature .........................-65C to + 150C Voltage on Any Pin with Respect to Ground.............................. -1.0 V +7.0V Maximum Operating Voltage................................. 6.25V DC Output Current .............................................. 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1-1.
Block Diagram
16384/32768 x 8
2
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
Table 1-1. Pin Capacitance (1 Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol COUT CIN Notes: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 1-2. DC Characteristics Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 IIL IOL VIL(1) VIH
(1)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Supply Current Standby Current Standby Current Standby Current Input Current Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage
Test Condition
Min 1.8 2.5 4.5
Typ
Max 5.5 5.5 5.5
Units V V V mA mA mA A A A A A V V V V
VCC = 5.0V at 20 MHz, SO = Open, Read VCC = 5.0V at 10 MHz, SO = Open, Read, Write VCC = 5.0V at 1 MHz, SO = Open, Read, Write VCC = 1.8V, CS = VCC VCC = 2.5V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0C to 70C -3.0 -3.0 -1.0 VCC x 0.7 3.6V VCC 5.5V 1.8V VCC 3.6V IOL = 3.0 mA IOH = 1.6 mA IOL = 0.15 mA IOH = 100 A VCC - 0.2 VCC - 0.8
9.0 5.0 2.2 0.2 0.5 2.0
10.0 7.0 3.5 3.0 3.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4
VOL1 VOH1 VOL2 VOH2 Notes:
0.2
V V
1. VIL min and VIH max are reference only and are not tested.
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Table 1-3. AC Characteristics Applicable over recommended operating range from TA = - 40C to + 85C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter SCK Clock Frequency Voltage 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 20 40 80 20 40 80 100 100 200 100 100 200 100 100 200 5 10 20 5 10 20 5 10 20 5 10 20 0 0 0 0 0 0 20 40 80 Min 0 0 0 Max 20 10 5 2 2 2 2 2 2 Units MHz
fSCK
tRI
Input Rise Time
s
tFI
Input Fall Time
s
tWH
SCK High Time
ns
tWL
SCK Low Time
ns
tCS
CS High Time
ns
tCSS
CS Setup Time
ns
tCSH
CS Hold Time
ns
tSU
Data In Setup Time
ns
tH
Data In Hold Time
ns
tHD
HOLD Setup Time
ns
tCD
HOLD Hold Time
ns
tV
Output Valid
ns
tHO
Output Hold Time
ns
4
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
Table 1-3. AC Characteristics (Continued) Applicable over recommended operating range from TA = - 40C to + 85C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter HOLD to Output Low Z Voltage 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 4.5-5.5 2.5-5.5 1.8-5.5 1M Min 0 0 0 Max 25 50 100 25 50 100 25 50 100 5 5 5 Units ns
tLZ
tHZ
HOLD to Output High Z
ns
tDIS
Output Disable Time
ns
tWC Endurance
(1)
Write Cycle Time
ms
3.3V, 25C, Page Mode
Write Cycles
Notes:
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
2.
Serial Interface Description
MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave. TRANSMITTER/RECEIVER: The AT25128B/256B has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL-OP CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128B/256B, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to "1". 5
8698B-SEEPR-3/10
Figure 2-1.
SPI Serial Interface
AT25128B/256B
6
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
3. Functional Description
The AT25128B/256B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-tolow CS transition. Table 3-1. Instruction Set for the AT25128B/256B
Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X 010 Operation Set Write Enable Latch Reset Write Enable Register Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
Instruction Name WREN WRDI RDSR WRSR READ WRITE
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 3-2.
Bit 7 WPEN
Status Register Format
Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
Table 3-3.
Bit Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1)
Read Status Register Bit Definition
Definition Bit 0 = "0" (RDY) indicates the device is ready. Bit 0 = "1" indicates the write cycle is in progress. Bit 1 = 0 indicates the device is not write enabled. Bit 1 = "1" indicates the device is write enabled. See Table 2-4 on page 9. See Table 2-4 on page 9.
Bits 4 - 6 are 0s when device is not an internal write cycle. Bit 7 (WPEN) See Table 3-5 on page 8
Bits 0 - 7 are "1"s during an internal write cycle.
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WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 2-4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR) Table 3-4.
Level 0 1 (1/4) 2 (1/2) 3 (All)
Block Write Protect Bits.
Status Register Bits BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25128B None 3000 - 3FFF 2000 - 3FFF 0000 - 3FFF AT25256B None 6000 - 7FFF 4000 - 7FFF 0000 - 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0". When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP pin is held low.
Table 3-5.
WPEN 0 0 1 1 X X
WPEN Operation
WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address to be read (Table 2-6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle.
8
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see Table 2-6 for the address key). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write cycle.
Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
Table 3-6.
Address Key
Address AN AT25128B A13 - A0 A15 - A14 AT25256B A14 - A0 A15
Don't Care Bits
9
8698B-SEEPR-3/10
4.
Timing Diagram (for SPI Mode 0 (0,0)
Figure 4-1.
VIH
Synchronous Data Timing
t CS
CS
VIL
tCSS t CSH
VIH
SCK
VIL
t SU
t WH
t WL
tH
VIH
SI
VIL
VALID IN
tV
t HO
t DIS HI-Z
VOH
SO
VOL
HI-Z
Figure 4-2.
CS
WREN Timing
SCK SI
WREN OP-CODE
SO
HI-Z
Figure 4-3.
CS
WRDI Timing
SCK SI
WRDI OP-CODE
SO
HI-Z
10
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
Figure 4-4.
CS
RDSR Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
Figure 4-5.
CS
WRSR Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
DATA IN
SI
INSTRUCTION
7
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Figure 4-6.
CS
READ Timing
0
1
2
3
4
5
6
7
8
23 24 25 26 27 28 29 30
SCK
BYTE ADDRESS
SI
INSTRUCTION
AN
...
A0
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
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8698B-SEEPR-3/10
Figure 4-7.
CS
WRITE Timing
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
DATA IN
SI
INSTRUCTION
15 14 13 ... 3
2
1
0
7
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Figure 4-8.
CS
HOLD Timing
t CD
t CD
SCK
t HD
HOLD
t HD t HZ
SO
tLZ
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AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
5. Ordering Code Detail
AT25128B-SSHL-B
Atmel Designator Shipping Carrier Option
B or blank = Bulk (tubes) T = Tape and Reel
Product Family
Operating Voltage
L = 1.8V to 5.5V
Device Density
128 = 128k 256 = 156k
Package Device Grade or Wafer/Die Thickness
H = Green, NiPdAu lead finish, Industrial Temperature range (-40C to +85C) U = Green, matte Sn lead finish, Industrial Temperature range (-40C to +85C) 11 = 11mil wafer thickness
Device Revision
Package Option
SS = X= MA = C= WWU WDT JEDEC SOIC TSSOP UDFN VFBGA = Wafer unsawn = Die in Tape and Reel
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8698B-SEEPR-3/10
6.
Part Markings
AT25128B-SSHL
Top Mark Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 5 D B L @ |---|---|---|---|---|---|---|---| * LOT NUMBER |---|---|---|---|---|---|---|---| | PIN 1 INDICATOR (DOT)
@ = Country of Y = SEAL YEAR 6: 2006 0: 7: 2007 1: 8: 2008 2: 9: 2009 3:
Ass'y 2010 2011 2012 2013 WW 02 04 :: :: 50 52 = = = : : = = SEAL Week Week :::: :::: Week Week WEEK 2 4 : :: 50 52
AT25128B-XHL
Top Mark PIN 1 INDICATOR (DOT) | * |---|---|---|---|---|---| A T H Y W W |---|---|---|---|---|---| 5 D B L @ |---|---|---|---|---|---|---| ATMEL L O T N U M B E R |---|---|---|---|---|---|---| @ = Country of Y = SEAL YEAR 8: 2008 2: 9: 2009 3: 0: 2010 4: 1: 2011 5: Ass'y 2012 2013 2014 2015 WW 02 04 :: :: 52 = = = : : = SEAL Week Week :::: :::: Week WEEK 2 4 : :: 52
AT25128B-MAHL
Top Mark |---|---|---| 5 D B |---|---|---| H L @ |---|---|---| Y X X |---|---|---| * | PIN 1 INDICATOR (DOT) Y = YEAR OF ASSEMBLY @ = Country of Ass'y XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,... AX, AY, AZ) Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013
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AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
AT25128B-CUL
Top Mark |---|---|---|---| 5 D B U |---|---|---|---| B Y M X X |---|---|---|---|---| * <-- PIN 1 INDICATOR
B= Y= M= XX=
Country of Origin One Digit Year Code One Digit Month Code TRACE CODE (ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK) (e.g. XX = AA, AB, AC,... YZ, ZZ) M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """""""" J = OCTOBER K = NOVEMBER L = DECEMBER
Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009
AT25256B-SSHL
Top Mark Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 5 E B L @ |---|---|---|---|---|---|---|---| * LOT NUMBER |---|---|---|---|---|---|---|---| | PIN 1 INDICATOR (DOT)
@ = Country of Y = SEAL YEAR 6: 2006 0: 7: 2007 1: 8: 2008 2: 9: 2009 3:
Ass'y 2010 2011 2012 2013 WW 02 04 :: :: 50 52 = = = : : = = SEAL Week Week :::: :::: Week Week WEEK 2 4 : : 50 52
AT25256B-XHL
Top Mark PIN 1 INDICATOR (DOT) | * |---|---|---|---|---|---| A T H Y W W |---|---|---|---|---|---| 5 E B L @ |---|---|---|---|---|---|---| ATMEL L O T N U M B E R |---|---|---|---|---|---|---| @ = Country of Y = SEAL YEAR 8: 2008 2: 9: 2009 3: 0: 2010 4: 1: 2011 5: Ass'y 2012 2013 2014 2015 WW 02 04 :: :: 52 = = = : : = SEAL Week Week :::: :::: Week WEEK 2 4 : :: 52
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At25256B-MAHL
Top Mark |---|---|---| 5 E B |---|---|---| H L @ |---|---|---| Y X X |---|---|---| * | PIN 1 INDICATOR (DOT) Y = YEAR OF ASSEMBLY @ = Country of Ass'y XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,... AX, AY, AZ) Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013
AT25256B-CUL
Top Mark |---|---|---|---| 5 E B U |---|---|---|---| B Y M X X |---|---|---|---|---| * <-- PIN 1 INDICATOR
B= Y= M= XX=
Country of Origin One Digit Year Code One Digit Month Code TRACE CODE (ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK) (e.g. XX = AA, AB, AC,... YZ, ZZ) M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """""""" J = OCTOBER K = NOVEMBER L = DECEMBER
Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009
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AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
7. Ordering Codes
AT25128B Ordering Information
Ordering Code AT25128B-SSHL-B (NiPdAu Lead Finish) AT25128B-SSHL-T(2) (NiPdAu Lead Finish) AT25128B-XHL-B(1) (NiPdAu Lead Finish) AT25128B-XHL-T(2) (NiPdAu Lead Finish) AT25128B-MAHL-T(2) (NiPdAu Lead Finish) AT25128B-CUL-T(2) (SnAgCu Ball Finish) AT25128B-WWU11L(3) Notes:
(1)
Voltage Range 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V
Package 8S1 8S1 8A2 8A2 8MA2 8U2-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube). 2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN and VFBGA 5k/reel). 3. Contact Atmel Sales for Wafer sales.
Package Type 8S1 8A2 8MA2 8U2-1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN) 8-ball, die Ball Grid Array Package (VFBGA)
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AT25256B Ordering Information
Ordering Code AT25256B-SSHL-B (NiPdAu Lead Finish) AT25256B-SSHL-T(2) (NiPdAu Lead Finish) AT25256B-XHL-B(1) (NiPdAu Lead Finish) AT25256B-XHL-T(2) (NiPdAu Lead Finish) AT25256B-MAHL-T(2) (NiPdAu Lead Finish) AT25256B-CUL-T(2) (SnAgCu Ball Finish) AT25256B-WWU11L(3) Notes:
(1)
Package 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V
Voltage Range 8S1 8S1 8A2 8A2 8MA2 8U2-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube). 2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN and VFBGA 5k/reel). 3. Contact Atmel Sales for Wafer sales.
Package Type 8S1 8A2 8MA2 8U2-1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN) 8-ball, die Ball Grid Array Package (VFBGA)
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AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
8. Packaging Information
8S1 - JEDEC SOIC
C
GND
4
NC
3
NC
2
NC
1
E
E1
5
6
7
8
L
O
SDA
SCL
NC
VCC
Top View
End View
e
b A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A1
A A1 b C D E1 E e L
1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 0
- - - - - - - 1.27 BSC - -
1.75 0.25 0.51 0.25 5.05 3.99 6.20 1.27 8
12/11/09
D
Side View
Notes: 1. These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
TITLE
GPC
DRAWING NO. 8S1
REV. E
Package Drawing Contact: packagedrawings@atmel.com
8S1, 8-lead, (0.150" Wide Body), Plastic Gull Wing Outline (JEDEC SOIC)
SWB
19
8698B-SEEPR-3/10
8A2 - TSSOP
4321
GND NC NC NC
Pin 1 indicator this corner
b E1 E e L1 D A2
A
Side View
SDA SCL NC VCC
5678
L
Top View
End View
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H.
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
D E E1 A A2 b e L L1
2.90 4.30 - 0.80 0.19 0.45
3.00 6.40 BSC 4.40 - 1.00 - 0.65 BSC 0.60 1.00 RE3
13.10 4.50 1.20 1.05 0.30 0.75
2, 5 3, 5
4
12/11/09 TITLE GPC DRAWING NO. 8A2 REV. D
Package Drawing Contact: 8A2, 8-lead, 4.4mm Body, Plastic Thin packagedrawings@atmel.com Shrink Small Outline Package (TSSOP)
TNR
20
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
8MA2 - UDFN
E
1
8
Pin 1 ID
2 3 4 7
D
6 5
C A2 A1 E2 b (8x)
8 7 6 5 1
A
Pin#1 ID (R0.10)
0.35
2
COMMON DIMENSIONS (Unit of Measure = mm)
D2
3 4
SYMBOL
MIN
NOM
MAX
NOTE
D E D2 1.40 1.20 0.50 0.00 - 0.30 0.18 0.20 E2 A A1 A2 C L e b K
2.00 BSC 3.00 BSC 1.50 1.30 0.55 0.02 - 0.152 REF 0.35 0.50 BSC 0.25 - 0.30 -
4/15/08
e (6x) L (8x) K
1.60 1.40 0.60 0.05 0.55 0.40 3
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229 for proper dimensions, tolerances, datums, etc. 2. The terminal #1 ID is a laser-marked feature. 3. Dimensions b applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
TITLE
GPC
DRAWING NO. 8MA2
REV. A
Package Drawing Contact: 8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally packagedrawings@atmel.com Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)
YNZ
21
8698B-SEEPR-3/10
8U2-1 - VFBGA
// 0.10 C 0.10 (4X) 0.08 C C
A1 Ball Pad Corner
D
A
Ob e
O0.15 M C A B O0.08 M C
B
A1 A2 A
Top View
Side View
A1 BALL PAD CORNER
2 1 A B e C (e1) D
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
A A1 A2 b D E e e1 d d1
0.81 0.15 0.40 0.25
0.91 0.20 0.45 0.30 2.35 BSC 3.73 BSC 0.75 BSC 0.74 BSC 0.75 BSC 0.80 REF
1.00 0.25 0.50 0.35
d (d1)
Bottom View
8 SOLDER BALLS
Notes: 1. This drawing is for general information. 2. Dimension 'b' is measured at the maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
2/25/08 TITLE GPC DRAWING NO. 8U2-1 REV. C
8U2-1, 8 ball, 2.35 x 3.73 mm Body, Package Drawing Contact: packagedrawings@atmel.com 0.75 mm pitch, VFBGA Package (dBGA2)
GWW
22
AT25128B/256B
8698B-SEEPR-3/10
AT25128B/256B
9. Revision History
Doc. Rev. 8698B 8698A Date 03/2010 12/2009 Comments Update Catalog Numbering Scheme. Update Ordering Information and package types. Initial document release.
23
8698B-SEEPR-3/10
Headquarters
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International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
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